An image display apparatus driven by the active-matrix driving method is known, and example of which is shown in FIG. 30. This type of image display apparatus comprises a pixel array ARY, a data signal line driving circuit SD and a scanning signal line driving circuit GD for driving pixel array ARY, and a timing signal generating circuit TIM for generating a timing signal inputted into data signal line driving circuit SD and scanning signal line driving circuit GD. A video signal DATA and a synchronizing signal SYN are inputted into data signal line driving circuit SD and timing signal generating circuit TIM, respectively.
FIG. 31(a) shows pixel array ARY, data signal line driving circuit SD, and scanning signal line driving circuit GD of FIG. 30 in a more specific manner. The image display apparatus includes a plurality of scanning signal lines GL.sub.j s and a plurality of data signal lines SL.sub.i s which cross with each other at right angles, and a matrix of pixels PIXs which is provided in such a manner that each pixel is encircled by two adjacent scanning signal lines and two adjacent data signal lines. In other words, a data signal line is provided for each column and a scanning signal line is provided for each row in the matrix.
In case of a liquid crystal display device, each pixel PIX comprises a pixel transistor SW serving as a switching element, and a pixel capacity composed of a liquid crystal capacity CL and an optional auxiliary capacity CS as shown in FIG. 31(b). In case of an active-matrix type liquid crystal display device, liquid crystal capacity CL and auxiliary capacity CS are generally placed in parallel to obtain a stable display. Auxiliary capacity CS is provided to minimize adverse effects resulted from a leak current of liquid crystal capacity CL or pixel transistor SW, changes in a pixel's displacement caused by a parasitic capacity such as a gate-source capacity of pixel transistor SW, or liquid crystal capacity CLs dependency on display data.
In FIG. 31(b), data signal line SL.sub.i is connected to one of the electrodes of the pixel capacity through the drain and source of pixel transistor SW serving as the switching element. Gate of pixel transistor SW is connected to scanning signal line GL.sub.j. The other electrode of liquid crystal capacity CL is connected to an opposing electrode with a liquid crystal cell in between, while the other electrode of auxiliary capacity CS is connected to either a common electrode line shared by all the pixels, or an adjacent scanning signal line.
As shown in FIG. 31(a), data signal line driving circuit SD samples an input video signal DATA in sync with a start pulse signal SPS. Then, data signal line driving circuit SD amplifies input video signal DATA in an adequate manner, and writes the same into each data signal line SL.sub.i. Scanning signal line driving circuit GD sequentially selects scanning signal lines GL.sub.j s in sync with start pulse signal SPS and controls an opening/closing action of the switching element in each pixel PIX, thereby writing video signal DATA written into each data signal line SL.sub.i into each pixel PIX to be held therein. Scanning signal line driving circuit GD and data signal line driving circuit SD are driven by power sources VGH/VGL and VSH/VSL, respectively.
In other words, data signal line driving circuit SD outputs a video signal DATA to data signal line SL.sub.i for each pixel or each horizontal scanning period (1H line). When scanning signal line GL.sub.j is activated, pixel transistor SW is turned on, thereby allowing video signal DATA sent via data signal line SL.sub.i to be written into the pixel capacity. When scanning signal line GL.sub.j is de-activated, pixel transistor SW is turned off, thereby allowing the pixel to maintain the display.
Data signal line driving circuit SD is driven by either the dot sequential driving system or line sequential driving system. In the dot sequential driving system shown in FIG. 32, video signals DATAs are readily written into data signal line SL.sub.i s through sampling switches SWTs controlled by the outputs from scanning circuits (i.e., shift register SRs). Thus, the dot sequential driving system downsizes the driving circuit but shortens a writing time in turn, and therefore is not suitable for a large-sized screen. Sample switching SWT generally comprises a single transistor or two parallel transistors of different conduction types. However, it is preferable to use a sample switching SWT of the CMOS structure to enhance sampling capability and reduce video signal's level fluctuation.
On the other hand, in the line sequential driving system shown in FIG. 33, video signals DATAs are sampled during the horizontal scanning period, and a line of sampled video signals DATAs are transferred to each amplifier circuit AMP during a horizontal retrace line period and written into data signal line SL.sub.i during the following horizontal scanning period. Thus, the line sequential driving system increases the size of the driving circuit but secures a sufficiently long writing time, and therefore is suitable for a large-sized screen. FIGS. 34(a) and 34(b) show typical structures of amplifier circuit AMP: the operation amplifier type and the source follower type, respectively.
A typical structure of scanning signal line driving circuit GD is shown in FIG. 35. Here, an AND signal of an output signal from the scanning circuit (i.e., shift register SR) and a gate pulse GPS regulating the width of a scanning signal is amplified by a buffer circuit BUF and outputted to scanning signal line GL.sub.i.
Data signal line driving circuit SD shown in FIGS. 32 and 33 and scanning signal line driving circuit GD shown in FIG. 35 use shift registers SRs as the scanning circuits, whose structure is shown in FIG. 36. Each shift register SR in one stage comprises one inverter and two clocked inverter, so that start pulse signal SPS is steadily transferred to the next stage in sync with the rise and fall of a clock signal CLK.
Besides shift register SR, a decoder type circuit can serve as the scanning circuit, and an example of which is shown in FIG. 37. This type of circuit serves as the scanning circuit by outputting an AND signal of a plurality of address signals A1, A2, . . . or their inverse signals /A1, /A2, . . . , in other words, the decoder type circuit serves as the scanning circuit by inputting a different address signal to each stage.
Here, /A1 represents an inverse signal of address signal A1, which is indicated in the drawing as: EQU A1(/A1=A1).
The inverse signals are indicated in the same manner below.
In most of the conventional active-matrix type liquid crystal display devices, the switching element of a pixel section comprises an amorphous silicon thin film transistor formed on a glass substrate, and the switching elements of scanning signal line driving circuit GD and data signal line driving circuit SD comprise a plurality of outboard driver ICs.
In contrast, to meet the recent demands for a more downsized, reliable, inexpensive image display apparatus, there has been developed a technique for monolithically assembling scanning signal line driving circuit GD, data signal line driving circuit SD, and pixel array ARY on a single substrate. In this technique, a field effect transistor using a silicon thin film of single crystal or non-single crystal (e.g., polycrystal or amorphous) is used as an active element. A polycrystalline silicon thin film transistor is used in most of the practical applications, because it can cover a large area and produce a sufficient high-power for driving scanning signal line driving circuit GD and data signal line driving circuit SD. To further upsize the display screen and save the mounting costs, a trial device is formed atop of a polycrystalline silicon thin film placed on a glass substrate at a processing temperature below a point of glass distortion (approximately 600.degree. C.).
However, unlike a transistor formed on a single-crystalline silicon substrate used in an LSI or the like, the manufacturing process of the non-single-crystalline silicon thin film transistor such as the polycrystalline silicon thin film transistor has not been fully established. Thus, the non-single-crystalline silicon thin film transistor has a problem that it easily causes faults such as a short and line disconnection. Also, although it depends on a screen size, the size of a substrate is increased considerably when the driving circuit and pixel array are formed monolithically on the substrate, and so are the probabilities of faults.
Incidentally, faults referred herein include a defective dot, a defective line, and a defective plane. When there occurs a defective plane, such a failing image display apparatus is discarded as a defective item in most cases. Because the defective plane involves a number of faults and troubleshooting each fault, if possible at all, demands a great deal of money and manpower.
In contrast, a defective dot can be neglected in some cases. Because the defective dot is caused by a failing pixel and a small number of defective dots will not show. Nevertheless, the defective dot can be prevented by a method of troubleshooting a fault in the pixel switch. In an example method disclosed in Japanese Laid-Open Patent Application No. 5-66418(1993), transistors are provided in pairs in each pixel, so that a failing transistor can be disconnected from the driving circuit.
Unlike the defective dot, the defective line is easy to see, and therefore even a small number of defective lines should be corrected. Primary causes of the defective line are the faults in the data signal lines and scanning signal lines such as line disconnection and a short, and the faults in the data signal line driving circuit and scanning signal line driving circuit. Each of the data signal lines and scanning signal lines is a simple wire, whereas the data signal line driving circuit and scanning signal line driving circuit include a great number of elements, wires, and contacting areas. Thus, the driving circuits have higher probability of faults than the lines driven by these driving circuits. Further, as previously mentioned, there has been no establishment in the process of manufacturing the polycrystalline silicon thin film transistor for the data signal line driving circuit and scanning signal line driving circuit. Accordingly, such an incomplete manufacturing process has higher probabilities of faults compared with the manufacturing process of the driver IC formed on the single-crystalline silicon substrate.
Thus, reducing the defective lines, and in particular, reducing the fault ratio in the driving circuit are crucial to improve the yield of the image display apparatus. Therefore, parallel with the improvement of the manufacturing process in reducing the faults, a redundant technique must be adopted to enable the driving circuit to operate as if there were no fault in the event a fault occurs therein.
A detailed explanation of a conventional driving circuit will be given in the following. As shown in FIG. 6, a scanning signal line driving circuit includes a scanning circuit section comprising serially connected n latch circuits 241a-24na which correspond to output signal lines 241c-24nc, respectively. Latch circuit 241a in the first stage is connected to a scanning signal line 241b. Thus, latch circuit 241a receives a pulse signal through scanning signal line 241b and transfers the same to latch circuit 242a in the next stage through a scanning signal line 242b based on a clock signal inputted through a timing control signal line 250. Buffer circuits 241g-24ng are respectively connected to latch circuits 241a-24na in their output side, and output the pulse signals from latch circuits 241a-24na to output signal lines 241c-24nc, respectively.
A data signal line driving circuit is of the same structure except that sample holding circuits are respectively connected to latch circuits 241a-24na in their output side instead of buffer circuit 241g-24ng.
In the above-structured conventional scanning signal line driving circuit or data signal line driving circuit, an output from a unit circuit (i.e., latch circuit) is inputted into another unit circuit in the next stage. Thus, a fault in an output of any stage makes the driving circuit inoperative. In addition, let a conforming ratio per stage be x and the number of outputs be n, then an overall conforming ratio of the driving circuit will be reduced to x.sup.n.
Since there has been an increasing demand for a larger, high-definition display screen, it is not surprising if a liquid crystal display or the like employing the above driving circuit includes as many as 1000 output stages. In this case, even a conforming ratio per stage is as high as 0.999(99.9%), a simple overall conforming ratio of the driving circuit is reduced to 0.999.sup.1000 .apprxeq.0.368 (36.8%). If the number of the outputs is slashed to half (500 stages), still the overall conforming ratio is reduced to 0.999.sup.500 .apprxeq.0.606(60.6%).
In short, a matrix type image display apparatus employing the conventional driving circuit has a problem that the overall conforming ratio of the driving circuit is lowered as the number of outputs increases, thereby making a large-sized or high-definition display apparatus expensive.
Especially, in case of a monolithic display device whose driving circuit and image display section are formed on a single substrate, components such as the driving circuit can not be replaced with a new one once they are assembled, meaning that a fault in the driving circuit triggers a fault in the display device.
Accordingly, Japanese Examined Patent Publication No. 2-13316(1990) discloses a display apparatus devised to eliminate the above problem. Herein, a scanning circuit section includes switching transistors made of the same silicon material making up the switching transistors connected to pixel electrodes, and the scanning circuit section is composed of a plurality of blocks of serially connected circuits featuring the same function; the blocks are aligned in parallel and the signal output terminals of the circuits in the same stage in all the blocks are directly connected to one of conducting wires forming the image display section.
More precisely, as shown in FIG. 7, latch circuits 241a'-24na' are respectively provided in parallel with latch circuits 241a-24na in the scanning circuit section. For example, latch circuit 241a and latch circuit 241a' in the first stage are connected directly to each other in the output side, and the pulse signals therefrom are inputted into latch circuit 242a and latch circuit 242a', in the next stage, respectively.
According to this structure, if latch circuit 241a fails, a wire 241d in the output side of latch circuit 241a is disconnected to isolate latch circuit 241a from the other terminals electrically, thereby enabling the driving circuit to operate as if there were no fault. In other words, the overall conforming ratio of the driving circuit is improved by allowing an operable latch circuit alone to output a pulse signal to another latch circuit in the next stage.
In this method, however, a latch circuit is always paired with the latch circuit provided in parallel. Thus, if both latch circuits 241a and 241a' fail, any other latch circuit can not serve as an alternate circuit, thereby making the driving circuit defective. Also, if there is a fault in any of the circuits beyond the scanning circuits, for example, buffer circuits 241g-24ng, although the output from the failing circuit does not affect the outputs of the others, it eventually makes the driving circuit defective.
In addition, since a plurality of blocks each having a plurality of unit circuits are aligned in parallel, if all the unit circuits operate properly, the unit circuits other than those forming a main block become useless. Moreover, since a plurality of identical unit circuits are aligned in the parallel blocks, there is a problem that the size of the driving circuit is inevitably increased.
To solve the above problem, a variety of techniques are proposed. For example, Japanese Examined Patent Publication No. 2-708(1990) discloses a liquid crystal display device, in which a pair of peripheral driving circuits are provided symmetrically with a display area in between, and the pair of the peripheral driving circuits are connected to a signal wire of the same portion in the display area.
Also, Japanese Examined Patent Publication No. 6-14253(1994) discloses a liquid crystal display device, in which a pair of scanning signal line driving circuits are provided symmetrically with a display area in between, and the outputs of shift register cells, one from each driving circuit, are connected to each other to be further connected to one scanning single line. When any of the shift register cells fails, the failing cell alone is laser-trimmed and separated from the driving circuit to enable the driving circuit to operate as if there were no fault.
The above liquid crystal display devices include a plurality of driving circuits, so that, if one driving circuit fails, another driving circuit can supply a signal to each pixel cell, thereby making it possible to produce a non-defective image.
Besides the above-explained image display apparatuses, Japanese Laid-Open Patent Application No. 6-67200(1994) discloses an image display apparatus, in which the scanning signal line driving circuits and data signal line driving circuits are provided respectively in pairs and each driving circuit is connected to all the wires. Thus, when one of the driving circuits in pairs fails, such a failing driving circuit is isolated electrically and the other driving circuit enables the image display apparatus to operate as if there were no fault.
However, when a pair of identical driving circuits are provided in this way, an area occupied by the peripheral circuits is increased two-fold, thereby causing an increase in the manufacturing costs. Moreover, since only a single fault can isolate the driving circuit entirely from the image display apparatus, both the driving circuits in paris are isolated if each has a fault, which makes it impossible to troubleshoot the faults, and thus puts a firm cap on the troubleshooting rate.
Another example is shown in Japanese Laid-Open Patent Application No. 6-83286(1994). Herein, the driving circuit is divided into a plurality of blocks each including two shift register series: regular and backup. According to this structure, when a regular shift register fails, the failing regular shift register is switched to a corresponding backup shift register to ensure a normal operation. This type of redundant technique is advantageous in that the driving circuit can operate as if there were no faults when the driving circuit has a number of faults in the shift registers substantially in as many blocks.
However, since this redundant technique is effective in troubleshooting the faults only in the shift registers, it must be combined with another technique to troubleshoot the faults in the entire driving circuit. Because the shift registers occupy a relatively small area in the driving circuit, the faults are more likely to occur in the circuits other than the shift registers. Therefore, a priority should be placed on to troubleshoot the faults in the other circuits.
Additionally, compared with a transistor formed on a substrate made of single-crystalline silicon, the transistor formed monolithically on the polycrystalline silicon thin film generally retains a small mobility, and a low driving capability due to its high threshold voltage. As a result, the monolithic transistor makes it difficult to widen a band of a video signal, such as an increase in an amount of data or reproduction of a moving picture.
If the phase of the clock signal is shifted and a plurality of shift register series, for example, a shift register series A and a shift register series B, are operated in parallel as shown in FIG. 53(a), an apparent response speed can be increased two-fold as shown in FIG. 53(b).
However, if such circuits are provided in the above-explained manner to improve the yield, the number of elements is increased approximately two-fold and there occurs a problem that not only the manufacturing costs but also a non-display area on the display panel is increased.
Also, in a driving circuit having such a polyphase shift register circuit, if an input side and an output side of a failing shift register (i.e., shift register A2) are simply shorted as shown in FIG. 54(a), an output timing inputted into the output stage of shift register A1 is also inputted into the output stage of shift register A2. Thus, as shown in FIG. 54(b), not only the time series are transposed among the shift register series, but also a video signal which should have been outputted from shift register A2 is outputted from an unillustrated shift register A4 in the form of an output signal a.sub.4, thereby causing displacements of the video signal.